Note that the DesignWare Building Blocks IP installation must occur on a Linux or Solaris machine, but this IP library can subsequently be accessed for FPGA synthesis by Synplify Premier and Certify software on a PC running Windows or Linux. It is also recommended that you set the following to ensure that the tool is accessing the DesignWare Building Blocks and not a legacy library: set_option -enable_DesignWare 0
This enables all DesignWare Building Block and minPower components to be used.If using minPower components use: set_option -dw_library.These options can also be specified interactively via the Certify/Premier GUI from the Verilog/VHDL tab. On the machine on which you are running Synplify Premier/Certify, configure the DesignWare license server by setting the variable Include the following in your Synplify Premier/Certify TCL file to specify the DC root installpath and then enable the DesignWare Building Block IP to be accessed.If you are using DesignWare Building Block IP, let Synplify Premier and Certify FPGA synthesis tools know where the DesignWare Library is located.
Accessing DesignWare Building Block from Synplify Premier and Certify
